1. Field of the Invention
The present invention relates to a semiconductor memory device and, more particularly, to a semiconductor memory device having a burst mode feature and adapted to operate with a low power dissipation.
2. Description of the Related Art
Pipeline burst static random access memory (PBSRAM) devices having a burst mode feature have taken a vital role in the rapid improvement of the performance of personal computers in recent years, as they are used as second cache memories. Almost 100% of currently available note-type personal computers including home-use personal computers are provided with one or more PBSRAM devices. PBSRAM devices are required to operate for processing data at a high speed and with a low power dissipation particularly in the case where they are used in note-type personal computers. The term "burst mode features" refers to a feature of carrying out a burst operation of fetching an external start address, thereafter internally and automatically generating the next address and subsequently reading from/writing in the memory circuit. For instance, if the starting address is 1, addresses 1, 2, 3, 4, . . . will be sequentially generated. While the data of the starting address will be output in several cycles, the data of each of the subsequent addresses will apparently be output in one cycle.
A PBSRAM device of the type under consideration that is used as a cache memory is constructed by a synchronous type memory circuit for holding data in synchronization with an external reference clock signal.
A first prior art semiconductor memory device includes a buffer constructed by a plurality of inverters for receiving an external input signal, and a memory circuit constructed by a plurality of memory elements driven by a reference clock signal. This will be explained later in detail.
In the first prior art semiconductor memory device, however, even in a burst operation which does not need the operation of the buffer the buffer always operate, which increases the power dissipation.
In a second prior art semiconductor memory device, an enable signal is a used to suspend the supply of the clock signal, thus decreasing the power dissipation. That is, the buffer constructed by inverters of the first prior art device is replaced by a buffer constructed of NAND circuits. Also, an NAND circuit is provided to mask the clock signal in response to the supply of the enable signal. The NAND circuits of the buffer also mask input signals to the memory circuit. This will also be explained later in detail.
In the second prior art semiconductor memory device, however, it is difficult to internally generate the enable signal to be used exclusively for controlling the clock signal and the memory circuit. Also, since a central processing unit (CPU) is also in a power down state when the enable signal is generated, the CPU is required to issue an additional control signal to be used exclusively for reducing the power dissipation if the power dissipation has to be reduced further.
In a third prior art semiconductor memory device, an enable signal is generated internally to suspend the supply of the clock signal to the memory circuit whenever necessary. For realizing this, a first latch circuit 8 for storing the enable signal and a second latch circuit for latching the output of the first latch circuit and outputting another enable signal are added to the elements of the first prior art device. This will also be explained later in detail.
In the third prior art semiconductor memory device however, while the memory circuit for storing data such as address data and control data does not operate, the buffer for the memory circuit and the clock signal fed to the latch circuits for holding the enable signal operate, thus increasing the power dissipation.
In a fourth prior art semiconductor memory device, comparators for respectively comparing the input signals of the memory circuit with the output signals thereof are added to the memory circuit of the third prior art device (see JP-A-7-262002). This will also be explained later in detail.
Even in the fourth prior art semiconductor memory device the power dissipation is increased. In addition, the power dissipation is increased because the device included the comparators for finding out if any change occurs in the stored information in order to suspend the supply of the clock signal.